完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lai, Kuan-Ting | en_US |
dc.contributor.author | Wu, Kun-Long | en_US |
dc.contributor.author | Hu, Robert | en_US |
dc.contributor.author | Jou, Christina F. | en_US |
dc.date.accessioned | 2016-03-28T00:05:44Z | - |
dc.date.available | 2016-03-28T00:05:44Z | - |
dc.date.issued | 2014-01-01 | en_US |
dc.identifier.isbn | 978-1-4673-5225-3 | en_US |
dc.identifier.issn | en_US | |
dc.identifier.uri | http://hdl.handle.net/11536/129810 | - |
dc.description.abstract | This paper reports our 77GHz power-amplifier designs using WIN 0.1 mu m GaAs pHEMT process provided by the commercial WIN foundry. The first two stages of the power amplifier is made of common-source transistors for gain amplification, and then followed by two-and four-paralleled transistors where the 3dB two-way Wilkinson power splitters/combiners for large output power delivery are used. All the by-pass capacitors for drain and gate biases have been optimized to have small series impedance at W-band. The input DC-blocking capacitor is made coupled lines, which also functions as tuning circuit. With 2.5V and 350mA drain bias, the small-signal gain is 12dB, as measured on-wafer at room temperature; the output-referred 1dB compression point is 6dBm. With 3dBm input power, the saturated output power is around 8.6dBm. Good input- and output-port matching has also been observed. The chip size is 1000x2500 mu m(2) and it consumes 875mW. | en_US |
dc.language.iso | en_US | en_US |
dc.title | 77GHz Power Amplifier Design Using WIN 0.1 mu m GaAs pHEMT Process | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 XXXITH URSI GENERAL ASSEMBLY AND SCIENTIFIC SYMPOSIUM (URSI GASS) | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000366628701177 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |