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dc.contributor.authorLai, Kuan-Tingen_US
dc.contributor.authorWu, Kun-Longen_US
dc.contributor.authorHu, Roberten_US
dc.contributor.authorJou, Christina F.en_US
dc.date.accessioned2016-03-28T00:05:44Z-
dc.date.available2016-03-28T00:05:44Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4673-5225-3en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/129810-
dc.description.abstractThis paper reports our 77GHz power-amplifier designs using WIN 0.1 mu m GaAs pHEMT process provided by the commercial WIN foundry. The first two stages of the power amplifier is made of common-source transistors for gain amplification, and then followed by two-and four-paralleled transistors where the 3dB two-way Wilkinson power splitters/combiners for large output power delivery are used. All the by-pass capacitors for drain and gate biases have been optimized to have small series impedance at W-band. The input DC-blocking capacitor is made coupled lines, which also functions as tuning circuit. With 2.5V and 350mA drain bias, the small-signal gain is 12dB, as measured on-wafer at room temperature; the output-referred 1dB compression point is 6dBm. With 3dBm input power, the saturated output power is around 8.6dBm. Good input- and output-port matching has also been observed. The chip size is 1000x2500 mu m(2) and it consumes 875mW.en_US
dc.language.isoen_USen_US
dc.title77GHz Power Amplifier Design Using WIN 0.1 mu m GaAs pHEMT Processen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 XXXITH URSI GENERAL ASSEMBLY AND SCIENTIFIC SYMPOSIUM (URSI GASS)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000366628701177en_US
dc.citation.woscount0en_US
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