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dc.contributor.authorLin, HCen_US
dc.contributor.authorLin, HYen_US
dc.contributor.authorChang, CYen_US
dc.date.accessioned2014-12-08T15:02:40Z-
dc.date.available2014-12-08T15:02:40Z-
dc.date.issued1996-05-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/0038-1101(96)00172-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/1310-
dc.description.abstractIn this study, p-channel polycrystalline silicon-germanium thin-film transistors (poly-Si1-xGex TFTs) with different Ge contents in the channel layer were fabricated and characterized. A novel device process was developed to fabricate the test samples. The device structure utilized the in situ boron-doped poly-Si0.79Ge0.21 with an extremely low resistivity (below 2 m Omega cm) as the source/drain and the undoped poly-Si (or Si1-xGex) as the channel layer. It is observed that the addition of Ge atoms in the channel would significantly increase the amount or trap density at grain boundaries thus degrading the device performance. Based on these results, we recommend the use of poly-Si1-xGex source/drain to reduce the contact resistance but do not recommend that it is appropriate to replace poly-Si as the channel material of TFTs.en_US
dc.language.isoen_USen_US
dc.titleEffect of Ge incorporation on the performance of p-channel polycrystalline Si1-xGex thin-film transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/0038-1101(96)00172-4en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume39en_US
dc.citation.issue5en_US
dc.citation.spage645en_US
dc.citation.epage651en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.department奈米中心zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.contributor.departmentNano Facility Centeren_US
dc.identifier.wosnumberWOS:A1996UE25100004-
dc.citation.woscount1-
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