標題: | A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset |
作者: | Lai, CS Lee, CL Lei, TF Chern, HN 電子工程學系及電子研究所 電控工程研究所 Department of Electronics Engineering and Institute of Electronics Institute of Electrical and Control Engineering |
公開日期: | 1-五月-1996 |
摘要: | A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance. |
URI: | http://dx.doi.org/10.1109/55.491828 http://hdl.handle.net/11536/1316 |
ISSN: | 0741-3106 |
DOI: | 10.1109/55.491828 |
期刊: | IEEE ELECTRON DEVICE LETTERS |
Volume: | 17 |
Issue: | 5 |
起始頁: | 199 |
結束頁: | 201 |
顯示於類別: | 期刊論文 |