A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset

doi:10.1109/55.491828

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lai, CS	en_US
dc.contributor.author	Lee, CL	en_US
dc.contributor.author	Lei, TF	en_US
dc.contributor.author	Chern, HN	en_US
dc.date.accessioned	2014-12-08T15:02:40Z	-
dc.date.available	2014-12-08T15:02:40Z	-
dc.date.issued	1996-05-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/55.491828	en_US
dc.identifier.uri	http://hdl.handle.net/11536/1316	-
dc.description.abstract	A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.	en_US
dc.language.iso	en_US	en_US
dc.title	A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/55.491828	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	17	en_US
dc.citation.issue	5	en_US
dc.citation.spage	199	en_US
dc.citation.epage	201	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1996UH51200003	-
dc.citation.woscount	9	-
顯示於類別：	期刊論文

文件中的檔案：

A1996UH51200003.pdf

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。