| 標題: | 應用於物聯網與互補式金氧半電路之低寄生電阻/電容元件技術開發 Development of Device Technologies with Reduced Parasitic Resistance/Capacitance for Iot and Cmos Applications. |
| 作者: | 林鴻志 國立交通大學電子工程學系及電子研究所 |
| 關鍵字: | ; |
| 公開日期: | 2016 |
| 摘要: | |
| 官方說明文件#: | MOST105-2221-E009-144-MY3 |
| URI: | https://www.grb.gov.tw/search/planDetail?id=11889853&docId=488344 http://hdl.handle.net/11536/131877 |
| Appears in Collections: | Research Plans |
- Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap / Wei, Lan;Deng, Jie;Chang, Li-Wen;Kim, Keunwoo;Chuang, Ching-Te
- On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology / Chen, Jie-Ting;Lin, Chun-Yu;Ker, Ming-Dou
- 0.13-mu m RF CMOS and varactors performance optimization by multiple gate layouts / Ho, CC;Kuo, CW;Chan, Y;Lien, WY;Guo, JC
- Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology / Ker, MD;Jiang, HC;Chang, CY
- Ultra low-capacitance bond pad for RF applications in CMOS technology / Hsiao, Yuan-Wen;Ker, Ming-Dou
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