標題: Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
作者: Ker, MD
Jiang, HC
Chang, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: bond pad;high-speed I/O;low capacitance pad;parasitic capacitance
公開日期: 1-十二月-2001
摘要: A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad is constructed by connecting multilayer metals and inserting additional diffusion layers into the substrate below the metal layers. The metal layers except top metal layer are designed with special patterns, which have smaller area than that in the traditional bond pad. Both the additional diffusion layers and patterned metal layers are used to reduce the parasitic capacitance of bond pad. An experimental test chip has been designed and fabricated to investigate the reduction of parasitic capacitance of the bond pad. The bonding reliability tests on the fabricated bond pad, including the ball-shear and wire-pull tests, are also used to verify the bonding adhesion. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The new proposed bond pads can also keep the same good bonding reliability as that of a traditional bond pad.
URI: http://dx.doi.org/10.1109/16.974736
http://hdl.handle.net/11536/29226
ISSN: 0018-9383
DOI: 10.1109/16.974736
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 48
Issue: 12
起始頁: 2953
結束頁: 2956
顯示於類別:期刊論文


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