標題: Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications
作者: Ker, MD
Peng, JH
電機學院
College of Electrical and Computer Engineering
關鍵字: bond pad;leakage current;temperature cycling test;thermal shock test
公開日期: 1-九月-2004
摘要: In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-mum 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembled with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.
URI: http://dx.doi.org/10.1109/TCAPT.2004.831764
http://hdl.handle.net/11536/26447
ISSN: 1521-3331
DOI: 10.1109/TCAPT.2004.831764
期刊: IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES
Volume: 27
Issue: 3
起始頁: 452
結束頁: 460
顯示於類別:期刊論文


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