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dc.contributor.authorKer, MDen_US
dc.contributor.authorPeng, JHen_US
dc.date.accessioned2014-12-08T15:38:39Z-
dc.date.available2014-12-08T15:38:39Z-
dc.date.issued2004-09-01en_US
dc.identifier.issn1521-3331en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAPT.2004.831764en_US
dc.identifier.urihttp://hdl.handle.net/11536/26447-
dc.description.abstractIn the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-mum 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembled with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.en_US
dc.language.isoen_USen_US
dc.subjectbond paden_US
dc.subjectleakage currenten_US
dc.subjecttemperature cycling testen_US
dc.subjectthermal shock testen_US
dc.titleInvestigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applicationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAPT.2004.831764en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIESen_US
dc.citation.volume27en_US
dc.citation.issue3en_US
dc.citation.spage452en_US
dc.citation.epage460en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000223628600003-
dc.citation.woscount3-
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