Title: | Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits |
Authors: | Ker, MD Jiang, HC Chang, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Issue Date: | 2000 |
Abstract: | A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance. |
URI: | http://hdl.handle.net/11536/19332 |
ISBN: | 0-7803-6598-4 |
ISSN: | 1063-0988 |
Journal: | 13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS |
Begin Page: | 293 |
End Page: | 296 |
Appears in Collections: | Conferences Paper |