Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ker, MD	en_US
dc.contributor.author	Jiang, HC	en_US
dc.contributor.author	Chang, CY	en_US
dc.date.accessioned	2014-12-08T15:27:06Z	-
dc.date.available	2014-12-08T15:27:06Z	-
dc.date.issued	2000	en_US
dc.identifier.isbn	0-7803-6598-4	en_US
dc.identifier.issn	1063-0988	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19332	-
dc.description.abstract	A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.	en_US
dc.language.iso	en_US	en_US
dc.title	Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS	en_US
dc.citation.spage	293	en_US
dc.citation.epage	296	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000165305200055	-
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