Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 張俊彥 | en_US |
| dc.contributor.author | 鄭淳護 | en_US |
| dc.contributor.author | 邱于建 | en_US |
| dc.date.accessioned | 2016-12-20T05:04:27Z | - |
| dc.date.available | 2016-12-20T05:04:27Z | - |
| dc.date.issued | 2016-10-16 | en_US |
| dc.identifier.govdoc | H01L027/105 | zh_TW |
| dc.identifier.govdoc | H01L021/8239 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/132318 | - |
| dc.description.abstract | 一種記憶體結構，包括基底、第一介電層、導體層、鐵電材料層與電荷擷取層。第一介電層設置於基底上。導體層設置於第一介電層上。鐵電材料層與電荷擷取層堆疊設置於第一介電層與導體層之間。 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | 記憶體結構 | zh_TW |
| dc.type | Patents | en_US |
| dc.citation.patentcountry | TWN | zh_TW |
| dc.citation.patentnumber | 201637172 | zh_TW |
| Appears in Collections: | Patents | |
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