標題: A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process
作者: Luo, Zhicong
Ker, Ming-Dou
電子工程學系及電子研究所
生醫電子轉譯研究中心
Department of Electronics Engineering and Institute of Electronics
Biomedical Electronics Translational Research Center
關鍵字: Charge balance;current memory cell;high-voltage-tolerant;leakage current compensation;level shifter;stimulator
公開日期: Dec-2016
摘要: This paper presents a 4 x V-DD neuro-stimulator in a 0.18-mu m 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-mu A biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 mu A) The residual average dc current is less than 6.6 nA after shorting operation.
URI: http://dx.doi.org/10.1109/TBCAS.2015.2512443
http://hdl.handle.net/11536/133081
ISSN: 1932-4545
DOI: 10.1109/TBCAS.2015.2512443
期刊: IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Volume: 10
Issue: 6
起始頁: 1087
結束頁: 1099
Appears in Collections:Articles