完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Li, YM | en_US |
dc.contributor.author | Chou, HM | en_US |
dc.contributor.author | Lee, JW | en_US |
dc.date.accessioned | 2014-12-08T15:18:30Z | - |
dc.date.available | 2014-12-08T15:18:30Z | - |
dc.date.issued | 2005-09-01 | en_US |
dc.identifier.issn | 1536-125X | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TNANO.2005.851410 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13314 | - |
dc.description.abstract | In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowing, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire Fin FETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | coverage ratio | en_US |
dc.subject | device structure | en_US |
dc.subject | fabrication | en_US |
dc.subject | fin field-effect transistor (FinFET) | en_US |
dc.subject | gate capacitance | en_US |
dc.subject | nanodevice | en_US |
dc.subject | nanowire | en_US |
dc.subject | omega-shaped-gate | en_US |
dc.subject | on/off ratio | en_US |
dc.subject | process technique | en_US |
dc.subject | quantum correction model | en_US |
dc.subject | semiconductor devices | en_US |
dc.subject | subthreshold swing (SS) | en_US |
dc.subject | surrounding gate | en_US |
dc.subject | three-dimensional (3-D) simulation | en_US |
dc.subject | turn-on resistance | en_US |
dc.title | Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.doi | 10.1109/TNANO.2005.851410 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON NANOTECHNOLOGY | en_US |
dc.citation.volume | 4 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | 510 | en_US |
dc.citation.epage | 516 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | 友訊交大聯合研發中心 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.contributor.department | D Link NCTU Joint Res Ctr | en_US |
dc.identifier.wosnumber | WOS:000231809500005 | - |
顯示於類別: | 會議論文 |