標題: | A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs |
作者: | Li, YM Chou, HM 電信工程研究所 友訊交大聯合研發中心 Institute of Communications Engineering D Link NCTU Joint Res Ctr |
關鍵字: | adaptive computation;channel length;density gradient drift-diffusion model;double-gate MOSFET;drain-induced barrier height lowering;numerical simulation;on/off current ratio;quantum correction transport model;sub 10 run;subthreshold swing;system-on-a-chip (SOC);thickness of silicon film;threshold voltage;very large scale integration (VLSI) |
公開日期: | 1-九月-2005 |
摘要: | We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal-oxide-semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage (V-th), and drain-induced barrier-height lowering are numerically calculated for the device with different channel length (L) and the thickness of silicon film (T-si). Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs, T-si should be simultaneously scaled down with respect to L. From a practical fabrication point-of-view, a DG MOSFET with ultrathin T-si will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that L/T-si >= 1 may provide a good alternative in eliminating SCEs of double-gate-based nanodevices. |
URI: | http://dx.doi.org/10.1109/TNANO.2005.851440 http://hdl.handle.net/11536/13317 |
ISSN: | 1536-125X |
DOI: | 10.1109/TNANO.2005.851440 |
期刊: | IEEE TRANSACTIONS ON NANOTECHNOLOGY |
Volume: | 4 |
Issue: | 5 |
起始頁: | 645 |
結束頁: | 647 |
顯示於類別: | 會議論文 |