標題: | Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement |
作者: | Wu, Chung-Shiang Lee, Hui-Hsuan Chen, Po-Hung Hwang, Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Controller voltage scaling;digital buck converter;power-stage voltage swing scaling;switching loss reduction |
公開日期: | 二月-2017 |
摘要: | In this brief, we present a digital pulsewidth modulation buck converter with a switching loss reduction scheme to improve conversion efficiency at light load conditions. The proposed switching loss reduction scheme combines power-stage voltage swing scaling, transistor width scaling, and controller voltage scaling to reduce the dynamic power dissipation of the system. The power-stage voltage swing scaling also reduces the inductor current ripple at light load conditions, which extends the available output current range in the continuous conduction mode (CCM). A duty ratio estimation mechanism is implemented to provide a modulated signal with the correct duty ratio to control the output voltage. Experimental results demonstrate a 38% conversion efficiency improvement at a 50-mu A output current. In addition, the proposed circuit achieves a 96% peak efficiency with an output current ranging from 20 mu A to 30 mA in the CCM operation. |
URI: | http://dx.doi.org/10.1109/TVLSI.2016.2592537 http://hdl.handle.net/11536/133187 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2016.2592537 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 25 |
Issue: | 2 |
起始頁: | 783 |
結束頁: | 787 |
顯示於類別: | 期刊論文 |