完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Chien-Chihen_US
dc.contributor.authorWey, Chin-Longen_US
dc.contributor.authorChen, Jwu-Een_US
dc.contributor.authorLuo, Pei-Wenen_US
dc.date.accessioned2017-04-21T06:55:34Z-
dc.date.available2017-04-21T06:55:34Z-
dc.date.issued2015-11en_US
dc.identifier.issn1084-4309en_US
dc.identifier.urihttp://dx.doi.org/10.1145/2770872en_US
dc.identifier.urihttp://hdl.handle.net/11536/133373-
dc.description.abstractThe performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratiomismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.en_US
dc.language.isoen_USen_US
dc.subjectDesignen_US
dc.subjectPerformanceen_US
dc.subjectTheoryen_US
dc.subjectAnalog-to-digital converter (ADC)en_US
dc.subjectsuccessive-approximation-register (SAR) ADCen_US
dc.subjectunit capacitoren_US
dc.subjectcommon-centroiden_US
dc.subjectrouting-aware placementen_US
dc.subjectspatial correlationen_US
dc.titlePerformance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCsen_US
dc.identifier.doi10.1145/2770872en_US
dc.identifier.journalACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMSen_US
dc.citation.volume21en_US
dc.citation.issue1en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000366897700014en_US
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