用於植入式癲癇元件之低功率十位元每秒五十萬次取樣逐次漸進式類比數位轉換器

Abstract

由於先進的積體電路科技，讓醫療器材的微小化得以實現。植入式生醫元件已發展用來治療一些神經疾病。

本論文提出一個用於植入式癲癇元件之低功率十位元每秒五十萬次取樣逐次漸進式類比數位轉換器。用於植入式生醫元件之電路，需考慮到功率消耗的問題。晶片如果產生過多的熱，會導致人體組織溫度上升，並造成危險。因此，低功率為植入式生醫元件的設計重點之一。類比數位轉換器為植入式生醫元件中主要功率消耗的電路之一，如何壓低其功率消耗更為重要。首先，選擇逐次漸進式類比數位轉換器應用於植入式癲癇元件。逐次漸進式類比數位轉換器為最常應用於中等解析度、中等採樣速度之架構。在論文中提出一個有效率的電容陣列可以大幅減少功率消耗。首先，串聯二進位加權式的電容陣列，可以省下百分之五十的切換能量。再來，使用較有效率的切換方法更進一步省下功率消耗。所提出的電容陣列與傳統二進位加權式的電容陣列相比只需要原本功率消耗的百分之四十，並且保持相同的電容誤差表現。

量測結果則為85μW的功率消耗，44.1 dB的訊號對雜訊諧波比，以及7.03的有效位元數。

Because of the advanced IC technology, the microminiaturization of biomedical devices has been achieved. Implantable biomedical devices are used to cure some neural disease.

This paper presents a 1.8V, 10-bit 500-kS/s low power successive approximation (SAR) analog-to-digital converter (ADC) for implantable epilepsy devices in TSMC 0.18μm 1P6M CMOS process. In order to achieve low power design, an efficient capacitor array is proposed to significantly reduce power consumption. First, a binary weighted capacitor array is cascoded to reduce 50% switching energy. Then, part of the junction-splitting switching method is applied to further reduce power dissipation. The proposed capacitor array only consumes 40 % power dissipation of a conventional binary weighted capacitor array, and has the same capacitance mismatch performance.

Measurement results of the proposed SAR ADC show that the total power consumption is 85 μW, the signal-to-noise-distortion ratio (SNDR) of 44.1 dB, and the effective-number-of-bits (ENOB) is 7.03.