New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs

Abstract

This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate germanium-on-insulator (GeOI) p-MOSFETs through theoretical calculation by analytical solution of 3-D Poisson's equation corroborated with TCAD numerical simulation. It is found that, relative to the silicon-on-insulator counterpart, there exists a build-in negative substrate bias in the GeOI PFET. This built-in substrate bias, stemming mainly from the large discrepancy in bandgap between Ge and Si, pulls the carriers toward the channel/BOX interface and thus degrades the DIBL of the GeOI PFET beyond what permittivity predicts. This new mechanism has to be considered when designing or benchmarking tri-gate GeOI p-MOSFETs.