完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Chang, WJ | en_US |
dc.date.accessioned | 2014-12-08T15:18:35Z | - |
dc.date.available | 2014-12-08T15:18:35Z | - |
dc.date.issued | 2005-09-01 | en_US |
dc.identifier.issn | 1530-4388 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TDMR.2005.856500 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13375 | - |
dc.description.abstract | Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces with the low-voltage-triggered p-n-p (LVTp-n-p) device in CMOS technology is proposed. The LVTp-n-p, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the p-n-p device, is designed to protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The LVTp-n-p devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-mu m CMOS process have proven that the ESD level of the proposed LVTp-n-p is higher than that of the traditional p-n-p device. Furthermore, layout on LVTp-n-p device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35- and 0.25-mu m CMOS processes have proven that the ESD levels of the LVTp-n-p drawn in the multifinger layout style are higher than that drawn in the single-finger layout style. Moreover, one of the LVTp-n-p devices drawn with the multifinger layout style has been used to successfully protect the input stage of an asymmetric digital subscriber line (ADSL) IC in a 0.25-mu m salicided CMOS process. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | electrostatic discharge (ESD) | en_US |
dc.subject | human body mode (HBM) | en_US |
dc.subject | low-voltage-triggered p-n-p (LVTp-n-p) | en_US |
dc.subject | optical-beam-induced resistance change (OBIRCH) | en_US |
dc.subject | photon emission microscope (EMMI) | en_US |
dc.title | ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TDMR.2005.856500 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | en_US |
dc.citation.volume | 5 | en_US |
dc.citation.issue | 3 | en_US |
dc.citation.spage | 602 | en_US |
dc.citation.epage | 612 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000235070500035 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |