Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Panda, D. | en_US |
dc.contributor.author | Simanjuntak, F. M. | en_US |
dc.contributor.author | Tseng, T. -Y. | en_US |
dc.date.accessioned | 2019-04-03T06:40:01Z | - |
dc.date.available | 2019-04-03T06:40:01Z | - |
dc.date.issued | 2016-07-01 | en_US |
dc.identifier.issn | 2158-3226 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1063/1.4959799 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134143 | - |
dc.description.abstract | On the way towards high memory density and computer performance, a considerable development in energy efficiency represents the foremost aspiration in future information technology. Complementary resistive switch consists of two antiserial resistive switching memory (RRAM) elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption. Here we present a titanium oxide based complementary RRAM (CRRAM) device with Pt top and TiN bottom electrode. A subsequent post metal annealing at 400 degrees C induces CRRAM. Forming voltage of 4.3 V is required for this device to initiate switching process. The same device also exhibiting bipolar switching at lower compliance current, Ic <50 mu A. The CRRAM device have high reliabilities. Formation of intermediate titanium oxi-nitride layer is confirmed from the cross-sectional HRTEM analysis. The origin of complementary switching mechanism have been discussed with AES, HRTEM analysis and schematic diagram. This paper provides valuable data along with analysis on the origin of CRRAM for the application in nanoscale devices. (C) 2016 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). | en_US |
dc.language.iso | en_US | en_US |
dc.title | Temperature induced complementary switching in titanium oxide resistive random access memory | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1063/1.4959799 | en_US |
dc.identifier.journal | AIP ADVANCES | en_US |
dc.citation.volume | 6 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000382403600082 | en_US |
dc.citation.woscount | 11 | en_US |
Appears in Collections: | Articles |
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