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dc.contributor.authorLi, YMen_US
dc.contributor.authorChou, HMen_US
dc.contributor.authorLee, JWen_US
dc.contributor.authorLee, BSen_US
dc.date.accessioned2014-12-08T15:18:40Z-
dc.date.available2014-12-08T15:18:40Z-
dc.date.issued2005-08-01en_US
dc.identifier.issn0167-9317en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.mee.2005.03.044en_US
dc.identifier.urihttp://hdl.handle.net/11536/13414-
dc.description.abstractWe, in this paper, study the electrostatic characteristics and the gate capacitances for carbon nanotube (CNT) array field effect transistors (FETs). The explored CNT-array FET is with three configurations of gate electrode, the top gate, the wrap around gate, and the bottom gate. Taking the pitch distance of structures and the gate length of CNT FET into consideration, a three-dimensional (3D) electrostatic simulation are performed by using an adaptive finite volume method, where different gate capacitance are calculated and compared. It is found that there is at least a 20% difference in calculating the gate capacitance between the 2D and 3D modeling and simulations. Our 3D simulation shows that a wrap around gate gives the largest gate capacitance among structures. A bottom gate possesses the weakest gate controllability. Effects of the pitch distance and the gate length on the gate capacitances of CNT-array FET are investigated. Results of the 3D electrostatic simulations can be applied to estimate the magnitude of the on-current of CNT FETs. (c) 2005 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectcarbon nanotube arrayen_US
dc.subjectfield effect transistoren_US
dc.subjecttop gateen_US
dc.subjectwarp around gateen_US
dc.subjectbottom gateen_US
dc.subjectelectrostatic potentialen_US
dc.subjectgate capacitanceen_US
dc.subject3D modelingen_US
dc.subjectcomputer simulationen_US
dc.titleA three-dimensional simulation of electrostatic characteristics for carbon nanotube array field effect transistorsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/j.mee.2005.03.044en_US
dc.identifier.journalMICROELECTRONIC ENGINEERINGen_US
dc.citation.volume81en_US
dc.citation.issue2-4en_US
dc.citation.spage434en_US
dc.citation.epage440en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department友訊交大聯合研發中心zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentD Link NCTU Joint Res Ctren_US
dc.identifier.wosnumberWOS:000231964900042-
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