完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChang, Chia-Wenen_US
dc.contributor.authorLo, Kai-Yuen_US
dc.contributor.authorIbrahim, Hossameldin A.en_US
dc.contributor.authorSu, Ming-Chiuanen_US
dc.contributor.authorChu, Yuan-Huaen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2019-04-03T06:40:10Z-
dc.date.available2019-04-03T06:40:10Z-
dc.date.issued2016-04-01en_US
dc.identifier.issn1745-1353en_US
dc.identifier.urihttp://dx.doi.org/10.1587/transele.E99.C.481en_US
dc.identifier.urihttp://hdl.handle.net/11536/134154-
dc.description.abstractThis paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.en_US
dc.language.isoen_USen_US
dc.subjectall-digital phase-locked loopen_US
dc.subjectdigitally controlled oscillatoren_US
dc.subjectlow voltageen_US
dc.subjectspur suppressionen_US
dc.subjectlow jitteren_US
dc.subjectlow spuren_US
dc.titleA Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniquesen_US
dc.typeArticleen_US
dc.identifier.doi10.1587/transele.E99.C.481en_US
dc.identifier.journalIEICE TRANSACTIONS ON ELECTRONICSen_US
dc.citation.volumeE99Cen_US
dc.citation.issue4en_US
dc.citation.spage481en_US
dc.citation.epage490en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000381557900009en_US
dc.citation.woscount0en_US
顯示於類別:期刊論文


文件中的檔案:

  1. d5c38864b33fbf0ac31038a471256ada.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。