標題: A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
作者: Chang, Chia-Wen
Lo, Kai-Yu
Ibrahim, Hossameldin A.
Su, Ming-Chiuan
Chu, Yuan-Hua
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: all-digital phase-locked loop;digitally controlled oscillator;low voltage;spur suppression;low jitter;low spur
公開日期: 1-Apr-2016
摘要: This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.
URI: http://dx.doi.org/10.1587/transele.E99.C.481
http://hdl.handle.net/11536/134154
ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.481
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E99C
Issue: 4
起始頁: 481
結束頁: 490
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