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dc.contributor.authorKer, MDen_US
dc.contributor.authorHsu, SFen_US
dc.date.accessioned2014-12-08T15:18:40Z-
dc.date.available2014-12-08T15:18:40Z-
dc.date.issued2005-08-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2005.852728en_US
dc.identifier.urihttp://hdl.handle.net/11536/13419-
dc.description.abstractThe physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-mu m CMOS technology.en_US
dc.language.isoen_USen_US
dc.subjectholding voltageen_US
dc.subjectlatchupen_US
dc.subjectsilicon controlled rectifier (SCR)en_US
dc.subjectsystem-level electrostatic discharge (ESD) testen_US
dc.subjecttransient-induced latchup (TLU)en_US
dc.titlePhysical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD testen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2005.852728en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume52en_US
dc.citation.issue8en_US
dc.citation.spage1821en_US
dc.citation.epage1831en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000230802200021-
dc.citation.woscount31-
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