標題: Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
作者: Ker, MD
Hsu, SF
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: board-level noise filter;latchup;SCR;system-level ESD test;transient-induced latchup (TLU)
公開日期: 1-二月-2006
摘要: Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against the transient-induced latchup (TLU) under the system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structures and the ring oscillator circuit fabricated in a 0.25-mu m CMOS technology. Some board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products.
URI: http://dx.doi.org/10.1109/TEMC.2006.870681
http://hdl.handle.net/11536/12692
ISSN: 0018-9375
DOI: 10.1109/TEMC.2006.870681
期刊: IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY
Volume: 48
Issue: 1
起始頁: 161
結束頁: 171
顯示於類別:期刊論文


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