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dc.contributor.authorChiang, Chien-Hsuehen_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2017-04-21T06:55:15Z-
dc.date.available2017-04-21T06:55:15Z-
dc.date.issued2016-10en_US
dc.identifier.issn1551-319Xen_US
dc.identifier.urihttp://dx.doi.org/10.1109/JDT.2016.2561081en_US
dc.identifier.urihttp://hdl.handle.net/11536/134204-
dc.description.abstractIn this study, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display. The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a five-mask amorphous silicon process for thin-film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.en_US
dc.language.isoen_USen_US
dc.subjectAmorphous silicon gate (ASG) driveren_US
dc.subjectclocken_US
dc.subjectdrivingmethoden_US
dc.subjectfall timeen_US
dc.subjectflat panel display (FPD)en_US
dc.subjectminimum operation high voltageen_US
dc.subjectperformanceen_US
dc.subjectpoweren_US
dc.titleA Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industryen_US
dc.identifier.doi10.1109/JDT.2016.2561081en_US
dc.identifier.journalJOURNAL OF DISPLAY TECHNOLOGYen_US
dc.citation.volume12en_US
dc.citation.issue10en_US
dc.citation.spage1051en_US
dc.citation.epage1056en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000384300400010en_US
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