标题: | A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology |
作者: | Zhao, Yan Chen, Zuow-Zun Du, Yuan Li, Yilei Al Hadi, Richard Virbila, Gabriel Xu, Yinuo Kim, Yanghyo Tang, Adrian Reck, Theodore J. Chang, Mau-Chung Frank 交大名义发表 National Chiao Tung University |
关键字: | Bulk voltage tuning;frequency synthesizer;harmonic oscillator;injection locking;phase-locked loop (PLL);subsampling phase detector;terahertz;triple-push Colpitts oscillator (TPCO);triple-push oscillator (TPO) |
公开日期: | 十二月-2016 |
摘要: | This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power. |
URI: | http://dx.doi.org/10.1109/JSSC.2016.2601614 http://hdl.handle.net/11536/134297 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2016.2601614 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 51 |
Issue: | 12 |
起始页: | 3005 |
结束页: | 3019 |
显示于类别: | Conferences Paper |