用於頻率合成器及無線通訊之金氧半積體電路技術

Abstract

隨著通訊系統及互補式金氧半導體之快速發展，應用於當代無線通訊系統之收發器電路技巧仍然是被迫切需要。頻率合成技巧是一項在收發器裡面不可或缺的技術，主要是用來執行產生穩定且低雜訊之本地振盪信號(Local oscillator, LO)，或是用於直接調變(Direct modulation)傳送。這些頻率合成器必需要符合低成本、低功率及低電壓操作之單晶片設計，並且也要能滿足相位雜訊及切換速度之系統規格。於各式各樣的通訊系統中，頻率合成器將面對不同的挑戰需要去克服。一訊號源操作於sub-THz(0.1-1 THz)頻率範圍被需要應用於感測、進階影像及生化偵測等應用。同時，射頻電路也被嘗試數位化並與基頻電路整合。對於生活的品質來說，一個低尺寸(form factor)及低功率之收發器則被需要用於生醫電子。 有鑒於此，本論文將開發金氧半電路技巧於頻率合成技術與無線通訊系統去克服將面臨的挑戰。發展數位輔助之射頻電路而應用於sub-THz影像系統與無線個人區域網路。除此之外，一高整合度之無線收發器也完成於無線身體區域網路而讓其應用能更普及。主要的研究主題有四項，其包括：(1)設計與分析一個數位控制且可切換模式之駐波振盪器，能產生基頻與三倍頻信號於sub-THz頻帶; (2)設計與分析具數位可重組傳輸線之寬調節範圍數位控制振盪器(Digitally controlled oscillator, DCO)於無線高畫質傳輸; (3)一具數位正交信號校正於突波衰減之快速跳頻多頻帶超寬頻正交多頻分工系統頻率合成器; (4)一無參考信號源(reference-less)且具1 Mbps QPSK調變之單晶片無線接收器應用於無線身體感測網路。 本論文第二章首先探討各種頻率合成技術並探究其特點。直接、間接及數位頻率合成技巧將被介紹並總結其特點於此章節。 第三章，介紹電感電容共振腔式電壓控制振盪器(LC-tank voltage-controlled oscillator)之設計考量。接下來，提出一個38/114 GHz可切換模式且能同步鎖定之駐波振盪器(Standing wave oscillator, SWO)。三倍頻之輸出頻率可以被數位控制激發以操作於不同模式。實驗模型以低漏電65 nm互補式金氧半導體技術製造。結合同步鎖定技巧，於38 GHz偏移1 MHz頻率所量測之相位雜訊在鎖定前後分別為-102 dBc/Hz與-120 dBc/Hz。在模式1操作於38 GHz及模式3操作於114 GHz下，所消耗之功率於1.2 V之偏壓下分別為4 mA及20 mA，其晶片面積為720×880 μm2. 第四章，介紹電感電容共振腔式數位控制振盪器之設計考量。之後，設計完成一具75 kHz解析度之10 GHz電感電容共振腔式數位控制振盪器應用於全數位鎖相迴路。其更精細之頻率解析度可進一步藉由高速之合差調變器(ΔΣ modulator)達成。所量測於1 MHz偏移頻率之相位雜訊為-102 dBc/Hz，使用90 nm互補式金氧半導體技術製造其共消耗3.9 mW於1 V之偏壓下。除此之外，一使用線性可變電感之40 GHz且具14%調節範圍之數位控制放大器應用於60 GHz超寬頻系統也被介紹於此。藉著所提出之技術，寬調節範圍及多頻帶操作可以被完成而不犧牲其振盪頻率。使用90 nm數位互補式金氧半導體技術，其能涵蓋38.6 GHz至 43.4 GHz之操作頻率。自43 GHz所量測10 MHz偏移頻率之相位雜訊為-109 dBc/Hz，輸出功率為-11 dBm。此數位控制振盪器於1.2 V偏壓下共消耗19 mW。晶片面積為0.5 × 0.15 mm2。 第五章提出一使用直接頻率合成技巧之3至10 GHz、14個頻帶且具突波(Spurs)縮減之頻率合成器應用於多頻帶超寬頻正交多頻分工系統。基於單一個鎖相迴路及兩級混頻之架構，其能降低諧波混合(Harmonic mixing)與頻率拉扯(Frequency pulling)之效應以抑制突波產生。同時，於鎖相迴路之迴授路徑上也只需要除二除頻器。因此更精準之正交次諧波項 (I/Q sub-harmonics) 能夠被單旁波帶混波器(Single sideband mixer, SSB mixer)利用以產生14個載波頻率。經實驗結果，於正交信號校正後，鏡像突波(Image spur)可以被改善 22dB且抑制至-45 dBc以下。使用0.18 μm互補式金氧半導體技術製造，此晶片於1.8 V電壓供應下共汲取65 mA。晶片面積為2.5 × 2.2 mm2 且提供14個頻帶之正交相位輸出。 第六章描述一2.4 GHz無參考信號源之單晶片無線接收機具1 Mbps 正交信號相位調變(QPSK modulation) ，使用0.18 μm互補式金氧半導體技術製造。此接收器直接由接收的射頻信號中，完成本地振盪載波之回復與資料解調變，而不需要振盪器形式之參考源及額外之類比至數位信號轉換器(Analog to digital converter, ADC)於基頻。其整合低雜訊放大器(Low noise amplifier, LNA)、混頻器、本地振盪載波回復迴路(LO recovery loop)、後級放大器(Post amplifier)及數位解調變器(Digital demodulator)於單一晶片，於1.8 V電壓供應下共消耗20.4 mW。由回復之載波於2.432 GHz所量測到1 MHz偏移頻率之相位雜訊為-112 dBc/Hz。晶片面積為1.75 x 1.55 mm2。 第七章總結本論文之主要成果。對於未來之建議也於此章節闡述。

With the rapid development of communication system and CMOS technology, the circuit techniques of contemporary transceivers for wireless communication remain to be imperatively desired. The frequency synthesis technique is an essential technique in transceivers to perform a stable and high purity local oscillator (LO) generation, or direct modulation transmission. These synthesizers need to meet the stringent requirements of low cost, low power and low voltage monolithic implementation while also meeting the phase noise and switching transient specifications. For various communication systems, the frequency synthesizers have to face different challenges that need to be overcome. The signal source at sub-THz (0.1-1 THz) is required for sensing, advanced imaging or bio-agent chemical detection application. Also, the RF circuits are tried to be digitalized and to be integrated with baseband. For quality of life, a small form factor and low power transceiver is needed for healthy electronics. This dissertation develops the CMOS circuit techniques for frequency synthesis and wireless communications to conquer the encountered challenges. The digital assisted RF techniques are developed for sub-THz imaging system and wireless personal area network. Besides, a highly integrated wireless transceiver for wireless body area network is achieved to promote pervasive adaptations. There are four major topics in this dissertation, including: (1) the design and analysis of a digitally controlled switched-mode standing wave oscillator capable of generating fundamental and triple output frequency in the sub-THz range; (2) the design and analysis of wide tuning range digitally controlled oscillators with digitally reconfigurable transmission line for wireless high definition; (3) a fast hopping MB-OFDM UWB (multi-band orthogonal frequency division multiplexing) frequency synthesizer with digital I/Q calibration for spurs reduction; (4) a reference-less single chip wireless receiver for 1 Mbps QPSK demodulation applied in wireless body sensor network. Chapter 2 reviews various types of frequency synthesis techniques and explores their characteristics. The direct, indirect and digital frequency synthesis are introduced and summarized in this chapter. In chapter 3, the design considerations of a LC-type voltage controlled oscillator (VCO) are introduced. Furthermore, a 38/114 GHz switched-mode standing wave oscillator (SWO) capable of synchronous locking is presented. Triple output frequency can be excited by digital control of different mode operations. The experimental prototype was fabricated using a low leakage 65 nm CMOS technology. Incorporating a synchronous lock scheme, the measured phase noise from a 38 GHz carrier before and after the phase locked at 1 MHz offset are -102 dBc/Hz and -120 dBc/Hz, respectively. For the mode 1 operation at 38 GHz and mode 3 operation at 114 GHz, the experimental prototype consumes 4 mA and 20 mA , respectively, under a 1.2 V biasing voltage and with a chip size of 720×880 μm2. In chapter 4, the design considerations of a LC-type digitally controlled oscillator (DCO) are introduced. Afterwards, the LC-type DCO achieves a 75 KHz frequency resolution with 10 GHz operating frequency for an all digital PLL (ADPLL) is presented. The frequency resolution can be further enhanced by employing high speed dithering through a ΔΣ modulator. The measured phase noise is -102dBc/Hz at 1MHz offset, while consuming 3.9 mW from a 1V power supply using 90 nm CMOS technology. Additionally, a 40 GHz and 14% tuning range DCO using proposed linear variable inductor (VID) is introduced for 60 GHz UWB system. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in 90-nm digital CMOS process, the DCO is capable of covering frequency range from 37.6 to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10 MHz offset, and the output power is -11 dBm. The DCO core dissipates 19 mW from a 1.2-V supply. Chip size is 0.5 × 0.15 mm2. Chapter 5 demonstrates a 3-10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system using direct frequency synthesis technique. Based on a single phase locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. From experimental results, the image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18 μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm2 providing 14 bands I/Q phases. Chapter 6 describes a 2.4 GHz reference-less single chip wireless receiver for 1Mbps QPSK demodulation using 0.18 μm CMOS technology. The receiver accomplishes LO carrier recovery and data demodulation directly from the RF received signal without a need of resonator-based reference source and extra baseband ADC. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power consumption is 20.4mW from a 1.8 V power supply. The measured phase noise from a recovered carrier at 2.432 GHz is about -112 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm2. Chapter 7 summarizes the main results of this dissertation. The recommendations for future works are also addressed.