An implementation of performance-driven block and I/O placement for chip-package codesign

Abstract

As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was developed by IBM is better suited for I/O increase than the typical peripheral wire-bond design. One of the most important characteristics of flip-chip designs is that the I/O buffers could be placed anywhere inside a chip, just like core cells. Motivated by [14] in proposing various I/O planning constraints, we develop a block and I/O buffer placement method in wirelength and signal skew optimization (especially for differential pair signals), and power integrity awareness for chip-package codesign. The results have shown that our approach takes care of power integrity and outperforms [12] in weighted performance metrics optimization.