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dc.contributor.authorLu, Ming-Chingen_US
dc.contributor.authorWu, Meng-Chenen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorJiang, Hui-Ruen_US
dc.date.accessioned2017-04-21T06:49:39Z-
dc.date.available2017-04-21T06:49:39Z-
dc.date.issued2006en_US
dc.identifier.isbn0-7803-9781-9en_US
dc.identifier.issn2164-1676en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ICPP.2006.65en_US
dc.identifier.urihttp://hdl.handle.net/11536/134496-
dc.description.abstractUsing voltage island methodology to reduce power consumption for System-on-a-Chip SoQ designs has ecome more and more popular rec. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IEP) are widely used, it is necessary to optimize floorplanning/placement methodolo considering voltage islands generation to solve power anFcritical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in mosules.en_US
dc.language.isoen_USen_US
dc.titlePerformance constraints aware voltage islands generation in SoC floorplan designen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ICPP.2006.65en_US
dc.identifier.journalIEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGSen_US
dc.citation.spage211en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000242043200053en_US
dc.citation.woscount1en_US
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