考慮效能要求的限制及電壓島產生之低功率平面規劃方法

Abstract

近來，使用電壓島方法來最佳化系統單晶片功率消耗設計是個越來越熱門的潮流。目前大部分使用電壓島方法通常只在比較高的系統層級，但是因為階層式設計、矽智產的廣泛使用，要在單晶片上最佳化模組位置、供給電壓以解決電路中緊要路徑延遲的問題並配合控制單元以達到低功率消耗、小面積及低繞線阻塞的要求，使得平面規劃時產生可相配合的電壓島有其必要性。因此在這篇論文裡我們便提出考慮效能要求的限制及電壓島產生之低功率平面規劃方法，我們的方法具有良好的擴充性且實驗結果顯示我們的方法是有效的，而達到低功率消耗的目標。

Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs becomes more and more popular recently. At present, this approach is mostly considered in system-level architecture. For hierarchical design and reuse intellectual property (IP) are widely used, it is necessary to optimize the floorplanning/placement considering voltage island generation to solve critical path delay problems, reduce area and wirelength, furthermore we can cooperate with the power management unit to attain low power consumption. Therefore we proposes in this thesis a low power floorplanning/placement methodology considering performance constraints and voltage island generation. Our method is flexible and can be extended to hierarchical application, and the experimental results show our method is effective to meet the performance constraints and reduce the power dissipation.