完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Zuow-Zun | en_US |
dc.contributor.author | Li, Yilei | en_US |
dc.contributor.author | Kuan, Yen-Cheng | en_US |
dc.contributor.author | Hu, Boyu | en_US |
dc.contributor.author | Wong, Chien-Heng | en_US |
dc.contributor.author | Chang, Mau-Chung Frank | en_US |
dc.date.accessioned | 2017-04-21T06:49:21Z | - |
dc.date.available | 2017-04-21T06:49:21Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-5090-0635-9 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134570 | - |
dc.description.abstract | A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from - 88 to - 109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from - 16.8 to - 34.6dBc, when operating at 2.4GHz. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Digital PLL for Phase Noise Cancellation in Ring Oscillator-Based I/Q Receivers | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS) | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000392504700043 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |