標題: Integration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantation
作者: Chou, Yu-Che
Hsu, Chung-Chun
Chun, Cheng-Ting
Chou, Chen-Han
Tsai, Ming-Li
Tsai, Yi-He
Lee, Wei-Li
Wang, Shin-Yuan
Luo, Guang-Li
Chien, Chao-Hsin
材料科學與工程學系
電子工程學系及電子研究所
Department of Materials Science and Engineering
Department of Electronics Engineering and Institute of Electronics
關鍵字: Body-tied Ge FinFET;DIBL (drain-induced barrier lowering);implantation;retrograde-well
公開日期: 2016
摘要: In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I-ON/I-OFF ratio and lower junction leakage (4x10(-3)mu A/cm(2)). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6x10(-6)mu A/cm(2))as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I-ON/I-OFF ratio similar to 8x10(3) (I-S) than the conventional Ge FinFET (I-ON/I-OFF similar to 2x10 (3)).
URI: http://hdl.handle.net/11536/134636
ISBN: 978-1-5090-1493-4
期刊: 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)
起始頁: 142
結束頁: 144
顯示於類別:會議論文