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dc.contributor.authorWan, Chia-Chenen_US
dc.contributor.authorLuo, Guang-Lien_US
dc.contributor.authorHsu, Shu-Hanen_US
dc.contributor.authorHung, Kuo-Dongen_US
dc.contributor.authorChu, Chun-Linen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.contributor.authorSu, Chun-Junen_US
dc.contributor.authorChen, Szu-Hungen_US
dc.contributor.authorWu, Wen-Faen_US
dc.contributor.authorYeh, Wen-Kuanen_US
dc.date.accessioned2017-04-21T06:48:46Z-
dc.date.available2017-04-21T06:48:46Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-5090-0726-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/134681-
dc.description.abstractReplacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility {111} surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I-ON/I-OFF of 5x10(5), which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process.en_US
dc.language.isoen_USen_US
dc.titleSuspended Ge Gate-All-Around Nanowire nFETs with Junction Isolation on Bulk Sien_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW)en_US
dc.citation.spage130en_US
dc.citation.epage131en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000391250500055en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper