菱形鍺奈米線場效應電晶體與微波退火矽穿隧電晶體之製程技術與特性研究

Abstract

在本論文中，吾人就未來次十奈米金氧半場效應電晶體(MOSFET)尺寸微縮時，相關的製程技術發展與元件特性分析作一系列之研究及探討。其涵蓋內容包含了利用乾蝕刻製程技術發展出一種新穎的菱形(diamond-shaped)全包覆式(gate-all-around)鍺與鍺矽奈米線場效應電晶體，提供了鍺基電晶體在半導體技術演進中，元件尺寸微縮至十奈米節點以下的應用能力。另外，在鍺基電晶體閘極介電層微縮方面，利用原子層沉積系統(ALD)對鍺材料表面施以間歇性的臭氧(ozone)製程處理，得到了相當薄的二氧化鍺(GeO2)厚度，提供了降低鍺電晶體之閘極介電層等效厚度(EOT)的製程平台。而在後續的源/汲(source/drain)極的雜質活化製程上，使用微波退火(microwave anneal)技術降低熱預算(thermal budget)，抑制了雜質擴散的現象，提供了未來技術節點之元件製作時精確控制雜質輪廓的能力。此外，進一步地控制微波退火製程抑制離子佈值散射雜質的活化則可得到極為陡峭的接面，增加穿隧電晶體(TFET)的元件特性與微縮能力。 首先在菱形奈米線結構的形成上，利用三個乾式蝕刻製程步驟來完成菱形的鍺/鍺矽奈米線通道，此三個步驟只需調整不同的氯(Cl2)與溴化氫(HBr)氣體比例做等向性/非等向性(isotropic/anisotropic)蝕刻即可完成。探討其形成機制主要在於使用等向性乾式蝕刻時，{111}晶向的蝕刻速率較{110}及{100}晶向的蝕刻速率為慢，因此可得到{111}晶向在蝕刻中自我停止(self-stopped)的結果。而該製程可適用於鍺、鍺矽及矽材料。此新穎的元件結構具有以下的特徵：(1)通道係為[110]晶向且沿著具有四個鍺材料載子傳輸速度較佳的{111}晶面的通道表面；(2)利用乾式蝕刻去除鍺/矽界面中的錯位缺陷使其成為接近無缺陷的傳輸通道，進而可優化元件的操作特性；(3)菱形奈米線的形成只需傳統的top-down製程方式及鍺薄膜磊晶技術即可完成最重要的關鍵製程步驟；(4)菱形對角線之通道寬度定義可由曝光製程的光阻圖案精確的轉移，且奈米線的位置可藉由乾式蝕刻的控制，使之緊鄰或介於光阻下的硬質罩幕(hard mask)與矽基板之間。 在菱形全包覆式鍺與鍺矽奈米線場效應電晶體的元件特性探討中，藉由全包覆式閘極結構具有控制能力較佳的優勢、在{111}表面上的高載子傳輸速度性質、較低的介面態(Dit)、接近無缺陷的懸浮通道等特性，在n型與p型場效應電晶體都得到相當優良的電性表現，尤其在p型鍺基場效應電晶體上，獲得了具有創記錄的十的八次方的元件開關電流比。而在鍺的磊晶薄膜中加入10％的矽，更可以增加雜質活化量以及進一步地改善介面態，增加元件的操作電流及改善次臨界擺幅(subthreshold swing)。 本論文中，在降低高遷移率(high mobility)鍺通道材料的等效閘極介電層厚度的製程上，使用原子層沉積系統對鍺材料表面施以390°C的間歇性臭氧製程處理過程中，能促使氧化鍺(GeO)的揮發，進而得品質較佳且厚度為0.36奈米的二氧化鍺。而採用微波退火製程，在源/汲極活化的結果中可得到較低的介面態，進而分別得到n型及p型鍺通道鯺狀場效應電晶體(Ge FinFET)的次臨界擺幅分別為67.8mV/decade及72.9mV/decade的良好特性。而使用傳統的快速退火及CO2雷射退火則會增加介面態，使得次臨界擺幅變差。另外在微波退火製程應用於抑制了雜質擴散的優勢上，則是用三閘矽奈米線場效應電晶體驗證其具有抑制閘極引發之汲極穿隧電流(GIDL)的效果。 最後則是微波退火製程進一步地應用於未來低耗能元件製作的研究。適當調控微波退火製程，避免在源/汲極離子佈植時散射在閘極下方的雜質活化，可在源/汲極與閘極下方的通道間形成極為陡峭的接面，且藉由Arrhenius plot分析穿隧行為，顯示其擁有不錯的接面特性。而利用此微波退火技術製作多閘之矽穿隧電晶體(multi-gate Si Tunnel FET)元件，不僅可增加穿隧效率提高元件操作效能，更可以獲得該元件製作時尺寸的微縮能力。本論文中製作出閘極尺寸為32奈米的矽穿隧電晶體元件，且同時在n型與p型穿隧電晶體都得到相當優良的電性表現，擁有極高的開關電流比。

In this dissertation, we have investigated the process technologies and device characteristics for sub-10nm MOSFET applications. A feasible pathway to scale Ge NWFETs beyond the 10 nm node was proposed by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire (NW) FETs with four {111} facets. In-situ ALD O3 treated Ge surface has been demonstrated to improve the interface of Ge FinFETs by removing damages and roughness induced by fin dry etching. Using microwave annealing (MWA) for S/D dopant activation with low thermal budget suppressed the increase of the interface states. The advantages of MWA for dopant activation include low defect density compared to RTA, negligible dopant diffusion, and suppression of non-ideal straggle effect of ion implantation. The tunable diamond-shaped Ge NW was obtained through simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The different etching selectivity of surface orientations for Cl2 and HBr was employed for the three-step isotropic/anisotropic/ isotropic dry etching. The ratio of Cl2 and HBr, mask width, and Ge recess depth were crucial for forming the nearly defect-free suspended Ge channel through effective removal of dislocations near the Si/Ge interface. The fabricated Ge NWs possesses four {111} facets along the <110> direction. This technique could also be applied for forming diamond-shaped Ge0.9Si0.1 and Si NWs. The diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) NWFETs with four {111} facets were then fabricated. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs. The in-situ atomic layer deposition (ALD) ozone treated Ge surface and MWA have been combined to reduce interface damage and to scale EOT of Ge FinFETs. An atomically thin GeO2 interfacial layer of 0.36 nm is achieved. The superior subthreshold characteristics of 67.8 mV/dec. and 72.9 mV/dec. for Ge n- and p-FinFETs, respectively, were simultaneously obtained for the first time because of the surface smoothing effect of ALD ozone treatment, the interface trap density reduction and diffusionless dopant activation induced by MWA. Furthermore, the gate-induced drain leakage (GIDL) current can be effectively suppressed by using the MWA for the S/D dopant activation. MWA activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel field-effect transistors (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type and p-type Si-TFETs by using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 μA/μm, a large current ON/OFF ratio of > 5x107, and minimal short-channel effect by using VG =2 V and VD =1 V.