完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChang, Hua-Yuen_US
dc.contributor.authorJiang, Iris Hui-Ruen_US
dc.contributor.authorChang, Yao-Wenen_US
dc.date.accessioned2017-04-21T06:48:45Z-
dc.date.available2017-04-21T06:48:45Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4503-2730-5en_US
dc.identifier.issn0738-100Xen_US
dc.identifier.urihttp://dx.doi.org/10.1145/2593069.2593145en_US
dc.identifier.urihttp://hdl.handle.net/11536/134709-
dc.description.abstractMetal-configarable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional LCD problem has the nature of dynamic logical and physical costs for at spare gate arrays. Unlike existing functional E0 works, which perform technology snapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and imp between the logical LCD network and the physical spare array relation graph.en_US
dc.language.isoen_USen_US
dc.subjectEngineering change orderen_US
dc.subjectGate arrayen_US
dc.subjectTechnology mappingen_US
dc.titleFunctional ECO Using Metal-Configurable Gate-Array Spare Cellsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2593069.2593145en_US
dc.identifier.journal2014 51ST ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000346506400188en_US
dc.citation.woscount0en_US
顯示於類別:會議論文