Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yang, Ching-Wei | en_US |
dc.contributor.author | Chao, Shao-Heng | en_US |
dc.contributor.author | Su, Pin | en_US |
dc.date.accessioned | 2017-04-21T06:48:17Z | - |
dc.date.available | 2017-04-21T06:48:17Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.isbn | 978-1-4673-2848-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134764 | - |
dc.description.abstract | In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Grain boundary | en_US |
dc.subject | polycrystalline silicon | en_US |
dc.subject | stackable NAND flash | en_US |
dc.subject | BE-SONOS | en_US |
dc.subject | variability | en_US |
dc.subject | Voronoi | en_US |
dc.title | Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2012 12th Annual Non-Volatile Memory Technology Symposium | en_US |
dc.citation.spage | 12 | en_US |
dc.citation.epage | 15 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000392841300003 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |