標題: | Delay-Line Based Fast-Locking All-Digital Pulsewidth-Control Circuit with Programmable Duty Cycle |
作者: | Su, Jun-Ren Liao, Te-Wen Hung, Chung-Chih 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Fast-locking;programmable duty cycle;pulse-width control circuit |
公開日期: | 2012 |
摘要: | This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty-cycle. In comparison with prior art, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This study presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600MHz, and an input duty cycle ranging from 30 to 70%. It achieves a programmable output duty cycle ranging from 31.25 to 68.75% in increments of 6.25%. |
URI: | http://hdl.handle.net/11536/134772 |
ISBN: | 978-1-4673-2771-8 |
期刊: | 2012 IEEE Asian Solid State Circuits Conference (A-SSCC) |
起始頁: | 305 |
結束頁: | 308 |
顯示於類別: | 會議論文 |