全數位廣域且具可程式工作週期之脈寬調變電路

Abstract

當系統晶片的操作頻率快速的增加時，高速數位系統的設計關鍵著重在如何抑制時脈的偏斜以及抖動量，而時脈偏斜造成系統不同步的現象，嚴重影響電路運作的正確性，因此許多電路例如鎖相迴路(PLL)、延遲電路(DLL) 被用於同步系統中不同部分的電路。為了符合能在單晶片系統中達到高速訊號處理的要求，雙資料速率技術常被使用，像是雙資料速率記憶體以及高速動態電路。雙資料速率技術同時使用參考訊號的上升及下降緣來取樣信號以降低整體電路的操作速度，取樣的參考訊號需要精準的50%責任週期。因為在製程、電壓、以及溫度變異之下，輸出訊號的責任週期會被影響，這些差異會在系統運作上會產生嚴重的問題，所以如何產生精準的50%責任週期相當的重要。 本篇論文，第一顆晶片提出一個推估時脈週期演算法的責任週期校正電路，根據提出的演算法以及時間數位轉換電路，得到輸入訊號的週期代表相對應的延遲單元數量，然而從時間數位轉換電路得到的數位碼將會向右平移並控制延遲電路，達到廣域的操作頻率。台積電0.18微米CMOS 技術之脈寬調變電路，顯示此電路可操作頻率範圍為100MHz到600MHz，可輸入訊號之責任週期範圍為40%到70%。 第二顆晶片提出一個200MHz到1300MHz的全數位脈寬調變電路，採用Gated-Ring震盪器TDC偵測輸入信號的週期，然後根據需求的工作週期算出所需延遲時間得到最後的脈寬。責任週期校正電路可計算輸出責任週期且不須查表。採用兩種延遲電路減少硬體消耗並為維持相同的精確度。台積電0.18微米CMOS 技術之脈寬調變電路，顯示此電路可操作頻率範圍為200MHz到1300MHz，可輸入訊號之責任週期範圍為30%到70%，可輸出脈波之責任週期範圍為31.25%到68.75%，間距為6.25%。

When the operation frequency in SOC is increasing, the clock skew and pulsewidth variation may cause errors in all systems. In digital systems, many circuits, like phase-locked loop (PLL) and delay-locked loop (DLL), are required to synchronize and align clock. In order to meet the requirements of the high-speed operation for SOC systems, double date rate (DDR) technology, such as DDR SDRAM, is used to achieve the need. Because the positive and negation transition edges of the reference clock signal are utilized to sample the data in DDR technology, a precise 50% duty-cycle clock is important. With the process, voltage, and temperature (PVT) variation, it is hard to maintain 50% duty-cycle of clock signal, so many papers are committed to find a solution to meet the requirements. In this thesis, we propose two duty-cycle correction circuits. The first one is an All-Digital Wide-Range Duty-Cycle Corrector using a Period Estimation Algorithm. We use the proposed algorithm and a time-to-digital converter (TDC) to obtain the number of the delay cells passed within one period of the input clock. The codes from TDC will shift and control two delay lines to allow the circuit to operate over a wide frequency rage. The circuit was fabricated by the TSMC 0.18-µm CMOS process. It can operate from 100MHz to 600MHz frequency. The acceptable duty cycle of the input clock ranges from 40% to 70%. The simulated locked time needs 28 cycles for 1.2GHz input signal. The second one is a 200-1300 MHz all-digital duty-cycle programmable circuit using gated ring oscillator TDC. The gated ring oscillator TDC is used to detect the period of the input clock and calculate the corresponding delay to generate output clock with the desired duty cycle. A duty-cycle setting circuit calculates the desired output duty cycle without the need for a look-up table. Two kinds of delay lines are used to reduce hardware and maintain the same level accuracy compared with prior arts. The circuit was fabricated by the TSMC 0.18-µm CMOS process. The total power consumption for the entire duty-cycle programmable circuit is only 27mW, the input duty cycle ranges from 30 to 70%, and the programmable output duty cycle ranges from 31.25 to 68.75% in increments of 6.25%.