A Hardware-Efficient Deblocking Filter Design for HEVC

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DC Field	Value	Language
dc.contributor.author	Fang, Chih-Chung	en_US
dc.contributor.author	Chen, I-Wen	en_US
dc.contributor.author	Chang, Tian-Sheuan	en_US
dc.date.accessioned	2017-04-21T06:49:04Z	-
dc.date.available	2017-04-21T06:49:04Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-4799-8391-9	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.uri	http://hdl.handle.net/11536/134779	-
dc.description.abstract	This paper presents a hardware-efficient deblocking filter architecture for High Efficiency Video Coding (HEVC) to reduce visual artifacts at block boundaries. This design proposes an interleaved scheduling to reduce the intermediate data storage to be 1536 bits instead of whole 8192 bits. The implementation with 90 nm CMOS technology can support real-time deblocking operation of 7682x4320@30 fps under 141.5 MHz with only 31K gate count.	en_US
dc.language.iso	en_US	en_US
dc.subject	Deblocking filter	en_US
dc.subject	HEVC	en_US
dc.subject	VLSI architecture design	en_US
dc.title	A Hardware-Efficient Deblocking Filter Design for HEVC	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)	en_US
dc.citation.spage	1786	en_US
dc.citation.epage	1789	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000371471002018	en_US
dc.citation.woscount	0	en_US
Appears in Collections:	Conferences Paper