標題: Accelerating Manycore Simulation by Efficient NoC Interconnection Partition on FPGA Simulation Platform
作者: Ku, Wei-Chun
Chen, Tien-Fu
交大名義發表
National Chiao Tung University
公開日期: 2011
摘要: manycore architecture is the trend of system design. However, manycore simulators face the important issue than general multicore simulators is simulation speed. Several studies provide a FPGA simulation methodology to solve it, but they almost do it by providing a new internal design of core. And some of them don\'t care the correctness without interconnection simulation. This paper provides a PVCT module and NIP methodology to solve these two issues. According to our experiment, we could provide a 91.4 MIPS simulation performance averagely with Splash2 benchmark by three physical cores. The number of three is decided by capability of Xilinx XC2V8000 FPGA chip.
URI: http://hdl.handle.net/11536/134795
ISBN: 978-1-4244-8499-7
期刊: 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
起始頁: 316
結束頁: 319
Appears in Collections:Conferences Paper