完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hung, Chian-Chang | en_US |
dc.contributor.author | Chiu, Po-Lin | en_US |
dc.contributor.author | Huang, Yuan-Hao | en_US |
dc.date.accessioned | 2017-04-21T06:49:53Z | - |
dc.date.available | 2017-04-21T06:49:53Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-5271-2 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134860 | - |
dc.description.abstract | In this paper, we present a 128 similar to 2048-point variable-length FFT processor for 4x4 MIMO-OFDM systems. In general, we must use n FFT processors for the nxn MIMO-OFDM system, and only 1/r operation time is employed for radix-r pipeline butterfly processor. This increases hardware cost and reduces hardware efficiency in VLSI implementation. Therefore, we propose radix-4(2) algorithm to deal with four data sequences simultaneously and a butterfly sharing technique to improve the hardware utilization. The design and implementation results show that the proposed FFT processor can achieve 83.3MHz frequency with 3.19mm(2) core area using a standard 90nm technology. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A Variable-Length FFT Processor for 4x4 MIMO-OFDM Systems | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | en_US |
dc.citation.spage | 156 | en_US |
dc.citation.epage | 159 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000300486600040 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 會議論文 |