標題: | A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems |
作者: | Chen, Yuan Lin, Yu-Wei Tsao, Yu-Chi Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | dynamic voltage and frequency scaling (DVFS);fast Fourier transform (FFT);multiple-input multiple-output (MIMO);orthogonal frequency division multiplexing (OFDM) |
公開日期: | 1-五月-2008 |
摘要: | This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2(4) FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FITT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 x 1.88 mm(2). The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner. |
URI: | http://dx.doi.org/10.1109/JSSC.2008.920320 http://hdl.handle.net/11536/29532 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2008.920320 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 43 |
Issue: | 5 |
起始頁: | 1260 |
結束頁: | 1273 |
顯示於類別: | 會議論文 |