動態電流規劃之基於記憶體以及動態定址架構之多輸入輸出快速傅立葉轉換處理器實作

Abstract

隨著行動通訊迅速的發展下，多種不同的無線通訊規格日新月異，而在正交分頻多工技術裡面，快速傅立葉轉換(FFT)是一個占很大量的計算以及硬體之區塊。因此本篇著重於如何去設計處理器單元以及如何去配合無線通訊平台(WPU)進行各種不同規格之無線通訊之演算法，重點將著重在其對於點數彈性以及與記憶體如何溝通，所展現的便是記憶體以及動態定址式的快速傅立葉轉換(FFT)處理器。 在此所提供之快速傅立葉轉換處理器將可利用記憶體式架構，提供2-65536點數之需求，並有一優化之面積(220K gate count)以及SQNR(大於52dB)，並且能夠利用分配運算單元的方式，分配資源給多根天線，達到多重輸入以及輸出的效果，而考慮到與WPU之共用需求記憶體，利用了動態位址式架構，能夠動態的存取所需要之記憶體空間，利於記憶體規劃，能夠有效的利用最小的資源，達到最大的成果。 另外考量行動裝置的低耗電課題，提出一動態電流規劃架構(DCS)，改善傳統動態電壓規畫(DVS)針對單一元件無法提供有效臨界電流缺點．利用pMOS寬度對電流之線性關係，本論文之DCS電路架構採用八個大小遞增的pMOS單元，可調控出256種線性電流變化，在系統初始時，搭配二元搜尋法以及錯誤驗證器快速鎖定所需要之初始電流，在系統運算中則搭配時間數位轉換器以及最小位元驗證器在進行勘錯，動態調整電流，達到系統穩定運算所需之最低電流消耗．以達到降低系統耗電之目標。 本論文整合前述之快速傅立葉轉換處理器與DCS，提出一基於動態電流規劃之記憶體以及動態定址式的快速傅立葉轉換(FFT)處理器，其中快速傅立葉轉換之運算單元在25℃、1.0V之環境下若操作頻率在100MHz至1GHz之區間能節省34%至75%之功率消耗。

With the rapid development of mobile communications, the numbers of different wireless communication specifications occurs, and in an orthogonal frequency division multiplexing technology inside, fast Fourier transform (FFT) is a very large number of calculations hardware cell, Therefore the paper focus on how to design a processor unit and how to fit wireless communications unit (WPU) for a variety of different specifications of the wireless communication algorithms, the important point will focus on the flexibility and how to communicate with the memory, shows the memory and dynamic addressable based fast Fourier transform (FFT) processor. Proposed FFT processor will be able to take advantage of memory architecture, providing 2-65536 demand points, and has an optimization of the area (220K gate count) and SQNR (greater than 52dB), and use the reconfigurable process elements to fit multiple input and output, while taking into account the needs and the shared memory WPU, the use of a dynamic addressable architecture that can dynamically access the required memory space, which will help memory plan, can effectively with minimal resources to achieve maximum results. Another issue is low-power in mobile devices, proposed a dynamic current scaling (DCS), improvement the shortcomings of traditional dynamic voltage scaling (DVS), for it cannot provide an effective critical current to fit necessary. And based on relationship between pMOS width and current in linear ,the DCS circuit architecture combines of eight incremental size pMOSs to get 256 kinds of linear current changes. In the system initially, with a binary search, and the error detector quickly find the initial requires current. And in the system is operational, we use time-to-digital converter and least signification bit checker to correct and dynamic adjust the current to achieve system stability required for computing to achieve the goal of reducing system power consumption. This paper integrates the aforesaid FFT processor with DCS, propose a dynamic current scaling on memory and dynamic addressable based Fast Fourier Transform (FFT) processors, and use the process element of fast Fourier transform simulate at environment in 25 ℃ and 1.0V,operation of the frequency range from 100MHz to 1GHz then can save 34-75% of the power consumption.