A dynamic scaling FFT processor for DVB-T applications

Abstract

This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer 1 are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 4.84 mm(2). Power dissipation is about 25.2 mW at 20 MHz.