完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Liao, Chien-Wei | en_US |
dc.contributor.author | Lai, Sheng-Chih | en_US |
dc.contributor.author | Lue, Hang-Ting | en_US |
dc.contributor.author | Yang, Ming-Jui | en_US |
dc.contributor.author | Shen, Chin-Yen | en_US |
dc.contributor.author | Lue, Yi-Hsien | en_US |
dc.contributor.author | Huang, Yu-Fong | en_US |
dc.contributor.author | Hsieh, Jung-Yu | en_US |
dc.contributor.author | Wang, Szu-Yu | en_US |
dc.contributor.author | Luo, Guang-Li | en_US |
dc.contributor.author | Chien, Chao-Hsin | en_US |
dc.contributor.author | Hsieh, Kuang-Yeu | en_US |
dc.contributor.author | Liu, Rich | en_US |
dc.contributor.author | Lu, Chih-Yuan | en_US |
dc.date.accessioned | 2017-04-21T06:49:32Z | - |
dc.date.available | 2017-04-21T06:49:32Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-2784-0 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135009 | - |
dc.description.abstract | The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E<10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Reliability Study of MANOS with and without a SiO2 Buffer Layer and BE-MANOS Charge-Trapping NAND Flash Devices | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF TECHNICAL PROGRAM: 2009 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS | en_US |
dc.citation.spage | 152 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000272451000068 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 會議論文 |