標題: VLSI Architecture of Leading Eigenvector Generation for On-chip Principal Component Analysis Spike Sorting System
作者: Chen, Tung-Chien
Liu, Wentai
Chen, Liang-Gee
交大名義發表
National Chiao Tung University
公開日期: 2008
摘要: On-chip spike detection and principal component analysis (PCA) sorting hardware in an integrated multi-channel neural recording system is highly desired to ease the bandwidth bottleneck from high-density microelectrode array implanted in the cortex. In this paper, we propose the first leading eigenvector generator, the key hardware module of PCA, to enable the whole framework. Based on the iterative eigenvector distilling algorithm, the proposed flipped structure enables the low cost and low power implementation by discarding the division and square root hardware units. Further, the proposed adaptive level shifting scheme optimizes the accuracy and area trade off by dynamically increasing the quantization parameter according to the signal level. With the specification of four principal components/channel, 32 samples/spike, and nine bits/sample, the proposed hardware can train 312 channels per minute with 1MHz operation frequency. 0.13 mm(2) silicon area and 282 mu W power consumption are required in 90 nm 1P9M CMOS process.
URI: http://hdl.handle.net/11536/135024
ISBN: 978-1-4244-1814-5
ISSN: 1557-170X
期刊: 2008 30TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-8
起始頁: 3192
結束頁: +
Appears in Collections:Conferences Paper