標題: Timing-Constrained Yield-Driven Redundant Via Insertion
作者: Yan, Jin-Tai
Chen, Zhi-Wei
Chiang, Bo-Yi
Lee, Yu-Min
電信工程研究所
Institute of Communications Engineering
公開日期: 2008
摘要: In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.
URI: http://dx.doi.org/10.1109/APCCAS.2008.4746363
http://hdl.handle.net/11536/135038
ISBN: 978-1-4244-2341-5
DOI: 10.1109/APCCAS.2008.4746363
期刊: 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4
起始頁: 1688
結束頁: +
Appears in Collections:Conferences Paper