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dc.contributor.authorHuang, Yu-Chien_US
dc.contributor.authorChen, Hsin-Chaoen_US
dc.contributor.authorTai, Tin-Jongen_US
dc.contributor.authorChen, Ke-Horngen_US
dc.date.accessioned2017-04-21T06:49:38Z-
dc.date.available2017-04-21T06:49:38Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2604-1en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ASSCC.2008.4708749en_US
dc.identifier.urihttp://hdl.handle.net/11536/135041-
dc.description.abstractThis paper proposes a dual-section average (DSA) analog-to-digital converter (ADC) to achieve a closed-loop digital pulse width modulation (DPWM) DC-DC converter with performance compatible to that by the analog PWM converter. For a 2.4V input voltage, a regulated output voltage of 1.2V can provide output current of 600mA without any off-chip compensators. Besides, the output ripple can be reduced to about 8mV(p-p) by theoretical result. The test chip was fabricated in 0.35 mu m CMOS technology. Owing to the parasitic resistance, the output ripple of the experimental result is within 8mV(p-p). Furthermore, the transient recovery time is within 50 mu s when load current changes from 120mA to 600mA, or vice versa.en_US
dc.language.isoen_USen_US
dc.titleDual-Section-Average (DSA) Analog-to-Digital Converter (ADC) in Digital Pulse Width Modulation (DPWM) DC-DC Converter for Reducing the Problem of Limiting Cycleen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ASSCC.2008.4708749en_US
dc.identifier.journal2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCEen_US
dc.citation.spage145en_US
dc.citation.epage+en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000265155300037en_US
dc.citation.woscount0en_US
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