Reliability Study on Tri-Gate Nanowires Poly-Si TFTs under DC and AC Hot-Carrier Stress

Abstract

This work studies reliability after dc and ac hot-carrier stress of polysilicon thin-film transistors (poly-Si TFTs) with single-channel and ten-nanowire channels, respectively. For single-channel (S1) poly-Si TFT, the device characteristics degradation under ac hot-carrier stress is severer than dc stress. In addition, the V-th and SS variation increases with the frequency increasing from 1 K Hz to 1 MHz. On the contrary, for tennanowire channels (M10) tri-gate poly-Si TFT, the V-th and SS variation is much lower than the S1 TFT with different stressing frequency. These results indicate that the M10 TFT has less deep state generation after dc and ac stress. Because the M10 TFT has more effective NH3 plasma passivation than that of S1 TFT due to the ten split nanowire channels has wide NH3 plasma passivation area. Moreover, M10 TFT has robust tri-gate control can reduce the lateral electrical field and its penetration from the drain to reduce hot-carrier effect. In ac stress study, the device degradation is dependent on the pulse failing time rather than rising time. In temperature study, the device degradation is improved as the operation temperature increasing from 25 degrees C to 75 degrees C.